Graduate Validation Engineer - VHDL / C++
This job has now expired
The role will entail working in a small team, creating C++ models to aid in the validation of leading edge processors. Your responsibilities will include:-
*Development of C++ simulation models from architectural specifications
*Development of tests for proving models performs as expected/specified
*Providing feedback to architecture team - critical in aiding improvements in the design!
*A good degree (1st/2:1) preferably in Electronic Engineering or equivalent (i.e. a Software Engineering, Maths or Physics with an understanding or interest in the development of complex hardware systems)
*Some hands-on project experience in VHDL/Verilog as well as C++
*Mixed knowledge of hardware and software design
*Experience of Unix based systems would be useful but not essential.
This is a brilliant opportunity to join a company at the top of their game and work alongside some highly experienced engineers. The working environment is relaxed and friendly, so it's a great place to start your career.
To apply, please email your CV to firstname.lastname@example.org. Please make sure to include project details of your C++ work, as this is key!
Key words: We are looking for bright graduates to join an exciting semiconductor company near West London. Candidates must be degree qualified in Electrical/Electronic Engineering/Telecommunications or similar, with a mix of the following skills: Digital, hardware, software, IC, SoC, C, C++, matlab, labview, debug, test, ASIC, FPGA, design, verification, testbench, linux, unix, assembler, graduate.
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