Senior Logic Design and Validation Engineer - Contract - Germany
A world leading in wireless chipset development is currently recruiting for and experienced digital design engineer for an initial 6 month contract in Germany
You will have the overall responsibility for System Verilog development and validation activities of cutting edge CPU technology
Responsibilities
- Unit level architectural specification
- RTL coding
- Logic synthesis (Synopsys toolset)
- Performance verification and GL simulation
- Test plan development execution and debug
Essential Experience
- At least 3 years design experience with logic design using System Verilog
- 3 Years experience RTL simulation and debug
- Strong knowledge of CPU architecture
- Strong knowledge of ASIC design tools and flows
This is a long term project and start dates are available throughout June 6-9 month contracts will be offered with the potential for further renewals. Above market rates can be offered for exceptional candidates. Apply today with an updated CV and details of availability for more information and to be considered