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Senior ASIC Design Engineer - Verilog, DSP - Contract - Swiss

This job is no longer available

Recruiter
Optimus Search
Posted
23 May 2012
Closes
20 June 2012
Ref
ASICDESVERCONTSWISS
Contact
Sam Walker
Location
Switzerland
Job Function
Contract Type
Contract
Hours
Salary
€55 - €60 per hour

Further information

Senior ASIC Design Engineer - Verilog, DSP - Contract - Switzerland

Experienced senior digital design engineers are currently required by a market leading electronics consulting company to develop cutting edge ASIC technolology for medical devices.

You will join a highly talented and specialised digital design team and have the opportunity to work at all stages of the digital development flow.


Responsibilities

    • Block level specification
    • Design and coding using verilog language
    • Advanced functional verification
    • ASIC synthesis


Essential Experience

    • Excellent knowledge of low power digital design techniques
    • In depth knowledge of Verilog design language
    • Exposure to a range of ASIC/FPGA design tools
    • Knowledge of DSP architectures



June/July start dates are available, initial 6 month contracts will be offered with the potential for further extensions, apply today with an updated CV for a telephone interview

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