An exciting opportunity for a Verification Engineer to become part of a dynamic and motivated design team working with the designers to achieve full verification of the cores is available to talented digital IC/ASIC/FPGA engineers for a leading SoC IP developer.
Verification Engineer primary responsibilities
-Formulation of a comprehensive test plan
-Generation of a verification matrix
-Generation of multiple testing environments including:
-Function verification
-SystemVerilog/Specman
-Formal (assertion based) tests
Required Skills
-Experience of digital design verification techniques
-Exposure to either Specman / SystemVerilog, OVM, VMM, UVM etc
-VHDL or Verilog programming language
-Exposure to a range of ASIC verification tools
-1-7 years in a relevant technology position
-Scripting: Perl, TCL, make and cshell
If you would like to be considered for this position please forward your cv via application process
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