This is an opportunity for a Analog IC Layout Engineer to join a world leader in Semiconductor technology!
In this role you will be responsible for implementing physical layout and verification of integrated circuits in different fabrication processes. Primary application areas include mixed signal RF and Analog/Mixed Signal IC Design using CMOS, BCD and RF CMOS processes.
Responsibilities will include:
- Full-custom analog and mixed-signal layout implementation, including matching concerns
- Physical verification and parasitic extraction
- IC layout floor planning and interfacing of full-custom with standard cell parts
- IC top level physical database preparation (dummy patterns, antenna, etc)
- Top-level physical sign-off verification (DRC/LVS/ANT/ERC/LVL)
- Continuous improvement of design environment regarding full-custom layout tools
- Writing of scripts to extend and improve the design flow
- Layout task planning
- Support of circuit designers in physical implementation methodology and tools
The successful Analog IC Layout Engineer will have established experience in Analog IC Layout in CMOS, strong Cadence tools experience (Virtuoso, Virtuoso-XL, Assura) as well an understanding of Linux operating system and scripting languages (shell, TCl, Python, Skill).
Excellent communication skills required in English with German a plus and the ability to work well within a team.
Contact Leon at IC Resources to apply.
Key words: Semiconductor, Analog IC Layout, CMOS, BCD and RF CMOS, Physical verification, Cadence, shell, TCl, Python, Skill. Location: Austria.
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