Junior Analog IC Layout - Cadence - Contract - Belgium
An established semiconductor design consultancy is currently recruiting for an analogue IC layout engineer with good knowledge of Cadence design tools for an initial 2 month contract based in Belgium.
You will be working on top level cell layout for analog/RF blocks using cadence tools in CMOS proceses
Responsibilities
- Sub-circuit schematic entry simulation and layout
- Work on the layout based on schematics from the design team ensuring it is LVS/DRC compliant
- Optimise the layout from a performance and area perspective
- Work closely with designers and lead layout engineers on new product development
Essential Experience
- 1-2 years experience in analog IC layout techniques
- Good knowledge of Cadence layout tools (Virtuoso, Virtuoso XL)
- Analogue transistor background
This is an excellent opportunity for a young graduate to gain experience working with a leading name in the semiconductor industry. This is a very urgent requirement and immediate starters are preferred, apply today with an updated CV for more information and to be considered