A System Design Methodology Engineer with excellent Virtual Prototyping and System Level Design Flow skills (systemC, C++, ESL Tools) is sought for a challenging and varied role developing leading system level design flows and improving methodologies for TLM verification. Excellent English language skills are required for this role.
This is a unique opportunity to work within a leading global group that is well respected within the industry for delivering innovative platforms across computing and communication segments including data centres, mobile and desktop personal computers, handhelds, embedded devices and consumer electronics. You will be working with the department that develops and markets innovative semiconductor products and solutions for wireless communications.
The ideal candidate will;
*Be degree qualified in Electronics/Physics/Computer Science/Engineering/Maths or similar with at least 4 years experience in a similar role
*Have experience with SystemC, C, C++, Perl, Tcl and ESL tools VaST Meteor, VaST Comet, Co-ware and Synopsys System Studio
*Have experience with Virtual Prototyping and System Level Design Flows and the tools used in chip development and/or software development
If this sounds like your ideal position then contact me for further details or to apply.
Keywords: Digital, ASIC, SoC, Hardware, Software, Verification, RISC, Specman e, Microprocessor, ARM, EDA, UNIX, LINUX, Tcl,Perl, systemC, C, C++, Perl, TCL, ESL, VaST Meteor, VaST Comet, Co-ware, Synopsys System Studio, Vera, Specman e, E Language, technical training, cadence, mentor graphics, Synopsys, Xilinix, Altera, Microsemi, Lattice, consultancy, customer-facing, FPGA, RTL, Design, OVM, VMM, UVM, SystemVerilog, VHDL, Verilog, testbench, Virtual Prototyping , System Level Design Flows , Chip development, Software development, Semiconductor, Munich Area, Germany, Europe
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