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Senior Digital Design Engineer - Verilog - Contract - Italy

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04 May 2012
01 June 2012
Sam Walker
Job Function
Contract Type
€50 - €55 per hour

Further information

Senior Digital Design Engineer - ASIC, Verilog - Contract - Italy

An established semiconductor consulting company is currently recruiting for an experienced digital design engineer, with excellent knowledge of Verilog langauage for a 3 month contract to be based in Northern Italy.

You will have the overall responsibility for the implementation and maintainance of test cases in a regression environment as well as generation of test patterns via Verilog simulation

Essential Experience

  • At least 3 years experience of Digital Design using Verilog
  • Unix environment with basic knowledge of Configuration Management
  • Basic knowledge of C (for test case development)
  • Ability to define test cases based on requirements

This is an urgent requirement you will be required to start at short notice. Apply today with an updated CV for more information and to be considered

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