Senior Digital Design Engineer - ASIC, VHDL - Contract -Belgium

Location
Belgium
Salary
€55 - €60 per hour
Posted
27 Apr 2012
Closes
25 May 2012
Ref
ASICHWCONTBELG
Contact
Sam Walker
Job Function
Design, Project Management
Contract Type
Contract
Hours
Full Time

Senior Digital Design Engineer - ASIC, VHDL - Contract - Belgium

An established consultancy developing digital ASIC technology for the consumer electronics industry is currently recruiting for an experienced digital design engineer with excellent knowledge of VHDL/Verilog language for an initial 6 month contract based in Belgium

You will have a strong background in DSP and expertise in digital ASIC design, you will play a key role in the development of ASIC utilising signal processing algorithms and highly optimised architectures

Responsibilities

  • Specification, simulation and optimisation of signal processing building blocks
  • Design of new signal processing algorithms
  • Design of ASIC architectures and optimisation of digital signal processing blocks
  • Integration of design into larger system context

Essential Skills

  • Digital ASIC design experience
  • Expertise in DSP algorithms as well as digital circuit optimisation techniques
  • Strong mathematical background

Start dates can be available throughout May initial 6 month contracts will be offered with the strong possibility of further renewals. Excellent rates can be offered, apply today with an updated CV and details of availability for more information and to be considered