IC Resources Ltd

Senior Mixed Signal Verification Engineer - Germany

Excellent Salary + Full Company Benefits
24 Apr 2012
22 May 2012
Clare O'Brien
Specialist Area
DSPs, Hardware
Contract Type
Full Time
A Senior Mixed Signal Verification Engineer with excellent advanced Verification skills (systemVerilog/OVM/UVM) is sought for a challenging and varied role involving advanced functional and formal verification. The successful Verification Engineer will work as part of a high calibre IC design team developing a range of ultra low-power microcontrollers. You will be tasked with defining the verification strategy of low power digital IPs, creating the verification environment, and collaborating with cross-functional IP teams throughout the complete development cycle.

The ideal candidate will;
*Be degree qualified in Electronics/Physics/Computer Science/Engineering/Maths or similar
*Have at least 3 years experience in Mixed-Signal ASIC Verification, with strong digital hardware design and verification skills using VHDL or Verilog, with particular expertise in constrained random systemVerilog/OVM verification.
*Have a desire to lead the verification efforts and drive forward the digital verification efforts throughout the company
*Have experience with state-of-the-art EDA software tools for simulation, layout and design flow, and be capable of performing Synthesis, Equivalence Checking and Static Timing Analysis on digital circuits

Any hands-on experience with complex mixed signal ICs or Digital Backend/Physical Design would be beneficial, but is not essential. You'll be working in a fast-paced, multicultural environment, where English is the main spoken language.

A competitive salary is on offer along with full company benefits and relocation allowance. Visa sponsorship is on offer for exceptional candidates.

If this sounds like your next career move then please contact me to apply or for further details.

Keywords: Digital, ASIC, SoC, Hardware, Software, Verification, RISC, Specman e, Microprocessor, ARM, EDA, UNIX, LINUX, Tcl, Perl, systemC, Vera, Specman e, E Language, FPGA, RTL, Design, OVM, VMM, UVM, SystemVerilog, VHDL, Verilog, testbench, Semiconductor, Munich Area, Travel, Germany, Europe

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