Analog IC Design Engineer required by UK - Edinburgh based client. Seeks experience in; PLL and DPLL for clock and data recovery/clock timing systems, power management chips (LDO regulator, DCDC switching converter, advanced digital power control). CMOS & BiCMOS, Cadence.
Our client, a successful and established company, has a requirement for a Senior Analog IC design Engineer with expertise in PLL and DPLL for clock and data recovery/clock timing systems.
You will join an existing team of experienced Engineers, where you will work on the design & development of a variety of circuits including High Bandwidth products like CDR, SERDES, PLL, DPLL, DLL for high speed reference clocks and data comms as well as power management chips (LDO regulator, DCDC switching converter, advanced digital power control) for mobile phones, PDAs, laptops and desktop PCs. Knowledge of low power RF transceivers (LNA, mixer, active filter, ADC/DAC) for low data rate remote activation may also be desirable.
The processes used will typically be 0.18um to 0.35um, CMOS & BiCMOS. A track record of delivering chips into production is essential with a working knowledge of issues like current limit protection, substrate noise suppression, ESD, latchup & IC Layout.
Industry degree qualified (or equivalent), the successful engineer will have established experience in power management, high speed comms or low power RF with a track record delivering chips into production. Strong Cadence tool knowledge required.
A competitive compensation and relocation package is on offer.
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