Senior Verification Engineer - ASIC - Malaysia
This job has now expired
This is an opportunity to work with one of Malaysia's leading technology providers for FPGA and ASIC design solutions. They provide an end-to-end IC Design service support to fabless design houses, electronics and semiconductor system companies, equipment manufacturers, and service providers, both on and off-site.
Responsibilities will include developing verification environments and test suites for full chip and block level testing, creating and/or integrating Verification IPs for various protocols, writing detailed testplans, developing testcases, running simulations and debugging functional errors as well as writing monitors, drivers, response checkers and SVA for correctness.
This exciting position requires a candidate with proven ASIC design verification and programming experience, using Verilog, PERL, TCL and C/C++, and strong system and block level reference modeling skills. Someone with knowledge and experience of Vera, E, assertion based verification, OVM VMM and systemVerilog and familiarity with embedded software/hardware co-simulation is highly desirable.
If you are interested in applying for this position please contact firstname.lastname@example.org or +44 (0) 118 988 1143.
Key words: Digital, ASIC, SoC, Hardware, Verification, RTL, Design, SystemVerilog, OVM, VMM, UVM, VHDL, Verilog, testbench, Semiconductor, Kuala Lumpur, Malaysia
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